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VIPER31SP
BATTERY CHARGER PRIMARY I.C.
ADVANCE DATA T YPE VIPER31SP V DSS 600 V In 1A R DS(on) 6.5
10
FEATURE s RECTANGULAR CHARACTERISTIC, WITHOUT OPTOCOUPLER s INTERNALLY TRIMMED CURRENT REFERENCE s FIXED SWITCHING FREQUENCY, ADJUSTABLE UP TO 150 KHZ s AUXILIARY VOLTAGE REGULATOR s SOFT START AND SHUT DOWN CONTROL s AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET "BLUE ANGEL" NORM (<1W TOTAL POWER CONSUMPTION) s UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS s INTEGRATED START UP SUPPLY s AVALANCHE RUGGED s OVERVOLTAGE PROTECTION s OVERTEMPERATURE PROTECTION s CYCLE BY CYCLE CURRENT LIMITATION s DEMAGNETISATION CONTROL BLOCK DIAGRAM
FB COMP
1
Power SO-10 DESCRIPTION VIPER31SP combines on the same silicon chip a PWM control dedicated to output current regulation together with an optimised high voltage avalanche rugged vertical power MOSFET (600V/1A). Typical applications cover battery chargers with constant current and constant voltage output characteristics, without any optocoupler between primary and secondary sections. Typical output power capability is 15 W in wide range condition and 30 W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the possibility to operate in no load condition with an input power as low as 1W. This feature insures the compliance towards "Blue Angel" norm and other similar ones.
OSC
DRAIN
VCC ON/OFF 2.6 V UVLO LOGIC R1 + R2 29 V R3 FF R4 Q PWM LATCH OSCILLATOR + +
OVERTEMP. DETECTOR
200 ns BLANKING + CURRENT REGULATION
+ 1.5 A
10 V REGULATOR
VDD
GND
CREF
CSENSE
DSENSE
SOURCE
SC12000
January 1998
1/16
VIPER31SP
ABSOLUTE MAXIMUM RATING
Symb ol V DS ID I DREV VCC VX IX I DSENSE V esd I D(AV) E D(AV) P tot Tj T s tg Parameter o Continuous Drain-Source Voltage (T j = 25 to 125 C) Maximum DC Drain Current Reverse DC Drain Current Supply Voltage Voltage Range Input (CSENSE, COMP, F B, OSC, CREF) Current Input (CSENSE, CO MP, F B, O SC, CREF Current Range Input (DSENSE) Electrostatic Discharge (R = 1.5 K C = 100pF) Avalanche Drain-Source Current, Repetitive or Not-Repetitive (T C = 100 o C, Pulse Width Limited by T J max) Avalanche Drain-Source Energy, Repetitive or Not-Repetitive (T C = 25 o C, Pulse Width Limited by TJ max) Power Dissipation at T C = 25o C Junction O perating Temperature Storage Temperature Value 600 Internally Limited -2.5 0 to 35 -03 to V DD 10 -10 to +10 2000 T BD T BD 62 -40 to 150 -65 to 150 Unit V A A V V mA mA V A mJ W C o C
o
THERMAL DATA
R t hj-ca se R th j-a mb. Thermal Resistance Junction-case Thermal Resistance Junction-ambient (Note1) Max Max 2.0 50
o o
C/W C/W
Note 1 : This thermal resistance corresponds to the standard mounting on a FR4 type printed circuit board.
CURRENT AND VOLTAGE CONVENTIONS
ICOMP
IDSENSE
IFB
IDRAIN
ICC 3 6 IDD 8 VCC VDD 2.6V 2 OSC FB 9 COMP 1 DSENSE 11 DRAIN
+
GND 10 CREF 4 ICREF VOLTAGE CONTROL
CURRENT CONTROL
IOSC
CSENSE 7 ICSENSE
SOURCE 5
VIPer31
ISOURCE VCOMP VFB VCC VDD VOSC VCREF VCSENSE VSOURCE RS VDRAIN VDSENSE
SC12020
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VIPER31SP
CONNECTION DIAGRAMS (top View)
PINS FUNCTIONAL DESCRIPTION DRAIN PIN: Integrated power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. SOURCE PIN: Integrated power MOSFET source pin. To be connected to an external current sense resistance which defines the output current value. GND Used as the signal reference for all low level signals. To be connected to the cold point of the current sense resistance. VDD PIN: It corresponds to the low voltage supply of the control part of the circuit. If Vdd goes below 6V, the circuit is shut down and the start-up current source is activated. The circuit resumes normal operation when the VDD voltage reaches 8V. An internal low drop linear regulator generates the VDD voltage from the VCC one, thus limiting its value at 10V. VCC PIN: This pin receives the auxiliary unregulated voltage from the main transformer, which can range from 7V up to 27V during normal operation. It delivers a start up current of 1.5mA during the shut down phase. The VCC pin is also connected to an internal 10V low drop regulator which provides the VDD voltage.
CSENSE PIN: Receives the voltage of the current sense resistor, representative from the power MOSFET drain current. CREF PIN: Serves as a reference for the peak power MOSFET drain current. It is also the output of the curent regulation function, which adjusts this reference voltage to keep the average output current constant. To be connected to an external filtering capacitor. DSENSE PIN: Detects the full demagnetisation of the main transformer, in order to drive the current regulation function. Refer to the application part for further details. It is also used to prevent any new turn on of the power MOSFET during the demagnetisation phase. FB PIN: This is the inverting input of the voltage mode error amplifier. This error amplifier is in charge of the limitation of the VCC voltage when the output current is lower than the nominal regulated one. COMP PIN: This is the output of the voltage mode error amplifier. An external R-C network connected between this pin and the FB pin defines the bandwidth of the voltage regulation loop, and insures the stability of the converter. OSC PIN: An RT-CT network must be connected on that pin to define the switching frequency. Note that despite the connection of RT to VDD, no significant frequency change occurs for VDD varying from 7V to 10V. It provides also a synchronisation capability, when connected to an external frequency source.
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VIPER31SP
ELECTRICAL CHARACTERISTICS (TJ = 25 oC, VCC = 12 V, unless otherwise specified) POWER SECTION
Symb ol BV DSS I DSS R DS( on) Parameter Drain-Source Voltage I D = 1 mA I D = 0.3 A o T J = 25 C o T J = 100 C ID = 0.3 A (see fig. 1) I D = 0.3 A (see fig. 1) V DS = 25 V Test Cond ition s VCOMP = 0 V V COMP = 0 V V SENSE = 0 V 6.5 10 V in = 300 V (1) V in = 300 V (1) 250 TBD TBD Min. 600 1 Typ . Max. Un it V mA ns ns pF
Off-State Drain Current V DS = 500 V Static Drain Source on Resistance Fall Time Rise Time Output Capacitance
tf tr C OSS
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symb ol I CCch I CC0 I CC1 I CC2 V DDo ff V DDo n VDDhyst V DDreg V DO I DDsc Parameter Start-up Charging Current Operating Supply Current Operating Supply Current Operating Supply Current Undervoltage Shutdown Undervoltage Reset Hysteresis Start-up Output Voltage Drop O ut Voltage Short Circuit Current Test Cond ition s V DD = 0 to V DDon (see fig. 2) F SW = 0 KHz (see fig. 2) F SW = 100 KHz F SW = 200 KHz (see fig. 2) (see fig. 2) (see fig. 2) (see fig. 2) V CC = 9 V (see fig. 2) V DD = 0 V IDD = T BD mA TBD TBD V DS = 250 V Min. Typ . -1.5 10 TBD TBD 6 8 2 T BD T BD T BD Max. Un it mA mA mA mA V V V V mV mA
OSCILLATOR SECTION
Symb ol F SW1 F SW2 V OSC V OSC
HI LO
Parameter Oscillator Frequency Initial Accuracy Oscillator Frequency Total Variation
Test Cond ition s R T = 8.2 K o T J = 25 C C T = 3300 pF (see fig.3)
Min. TBD TBD
Typ . 50 50 6.2 2.5
Max. T BD T BD
Un it KHz KHz V V
C T = 3300 pF R T = 8.2 K V DD = 7 to10 V (1)
Oscillator Peak Voltage (1) Oscillator Valley Voltage
(1) The peak and valley voltages are used internally by the voltage mode PWM. The sawtooth generated by the oscillator is compared to the COMP pin voltage to limit the duty cycle of the power mosfet switch. See block diagram on page 1.
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VIPER31SP
ELECTRICAL CHARACTERISTICS (continued) ERROR AMPLIFIER SECTION
Symb ol V REF V REF GBW A VOL I FB V COMP V COMP I COMP ICOMP
LO HI LO
Parameter Reference Voltage Temperaure Variation Unity G ain Bandwidth Open Loop Voltage Gain Input Bias Current Output Low Level Output High Level Output Low Current Capability Output High Current Capability
Test Cond ition s I COMP = 0 mA (see fig. 4) (see fig. 4) V FB = 5 V I COMP = -100 A I COMP = 100 A V COMP = 5 V V COMP = 5 V V FB = 5 V VF B = 0 V V FB = 5 V V FB = 0 V T J = 25 C
o
Min. TBD
Typ . 2.6 TBD 400
Max. T BD T BD
Un it V % KHz dB
TBD
50 2.5 1 9 3.5 -3.5 5
A V V mA mA
HI
CURRENT REGULATION SECTION
Symb ol V REG td Parameter Reference Voltage Current Sense Delay to Turn-off Test Cond ition s (see fig. 5) (See fig 1) (see fig. 6) 2.6 Min. 320 Typ . 350 Max. 380 350 Un it mV ns V
V DSENSEth Demagnetization Detector Threshold Voltage V DSENSEcl Demagnetization Detector Clamping Voltage
I DSENSE = 10 mA
(see fig. 6)
6
V
PROTECTION SECTION
Symb ol I Dl im tb V CClim VCChyst T SD T SDhyst Parameter Peak Drain Current Limitation Current Limitation Blanking T ime V CC Overvoltage Threshold V CC Overvoltage Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis RS = 0 RS = 0 V FB = 0 V V FB = 0 V (see fig. 8) (see fig. 8) Test Cond ition s (see fig. 9) (see fig. 9) (see fig. 7) (see fig. 7) 150 TBD 26 2 Min. 1 1.2 35 Typ . Max. 2.5 Un it A s V V
o
C C
o
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VIPER31SP
Figure 1: Switching Times
VDS 2.VIN tf VIN Tr ICC0
Figure 2: UVLO Logic Behaviour
ICC
VDDhyst
t ICCch ID VDD VDDreg td VCREF RS t
VDDoff
VDDon
VCC
VCC VDDreg+VDO
SC12030
SC12040
Figure 3: Switching Frequency Setting
Oscillator frequency vs Rt and Ct
1,000
+
500
VDD
300
Ct = 1.5 nF
RT OSC
Frequency (kHz)
200
Ct = 2.7 nF
0.62 VDD + S Q R +
100
Ct = 4.7 nF
CT 500
0.25 VDD
50
Ct = 10 nF
30 20 1 2 3 5 10 20 30 50
GND
Rt (k)
SC12050
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VIPER31SP
Figure 4: Error Amplifier Phase and Gain
(dB) 100
() 200
150
PHASE
50
GAIN
100 50
0
0 -50
Cload = 100pF
-50
-100
1
10
100
1k
10k
100k
1M
-150 10M
SC12060
Frequency (Hz)
Figure 5: Reference Voltage Measurement
3 6 8 8.2k 4.7uF 16V 2 OSC VIPer31 VCC VDD 2.6V FB
9 COMP
1 DSENSE
11 DRAIN
+
GND 10 CREF 4
CURRENT CONTROL
VOLTAGE CONTROL CSENSE 7 SOURCE 5
12V
3.3nF
Vreg
SC12070
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VIPER31SP
Figure 6: Demagnetisation Control Logic
DRAIN VDD 10A DSENSE VAUX VCC VDSENSEcl AUXILIARY WINDING GND Q + VDSENSEth SQ R RD 1 1 SOURCE EOD FROM PWM LATCH EOD VAUX VDSENSEth
t
0
t
SC12080
Figure 7: Overvoltage Protection
Figure 8: Overtemperature Protection
Tj Tsd
VCC VC Clim VCChyst
Tsdhyst
t ID
t
VCREF
t VDD VDDon
t
VDDoff
ID
t VCREF
t
t
SC12090
SC12100
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VIPER31SP
Figure 9: Blanking Time and Current Limitation
ID tb
Iout vs Uout curves for Vin = 100, 200, 300, 400 VDC, Ta = 25C 1
Figure 11: Typical Output Characteristics
IDlim
Iout (A) 0.8 Constant current operation (+/-2.5%)
Constant voltage operation (+/-7%)
t
0.6 Short circuit or Low voltage operation
ID
0.4
0.2
IDlim
0 5 10 15 Uout (V)
SC12120
t
SC12110
Figure 10: Typical AC/DC Adapter
F1 L FUSE T1 R1 N CTN C1 100nF BR1 + D1 IOUT STPS1100U 1A/600V C2 10uF 400V T2 C3 330uF 25V GND
D2
R2
1N4148 R3 27k R6
22 R4 22k C5 C4 R5 680k
10k 3 6 8 R8 8.2k 2 OSC U1 VIPer31 VCC VDD 2.6V FB
2.2n 9 COMP
1nF 1 DSENSE 11 DRAIN R7 680k
+
GND 10 CREF 4
CURRENT CONTROL
C6 2.2nF
VOLTAGE CONTROL CSENSE 7 SOURCE 5
C7 10uF 35V
C8 4.7uF 16V
R9
470 R10 2.7k C9 2.7nF C10 470nF R11 1.3
SC12130
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VIPER31SP
OPERATION DESCRIPTION : This device is intended to be used in off line AC/DC adapter where the desired output characteristic must present a rectangular characteristic. For output voltage values lower than a fixed value, the average output current must be constant, whatever are the input or output voltages. If the output current consumed by the load is lower than the previous constant current value, the output voltage value must be limited. In addition, the device provides protection against output short circuits and overtemperature events. The two modes of operation are described in the following paragraphs. Figure 10 presents a typical application of which the output characteristic can be seen on figure 11. topology cannot be easily kept constant, as it depends on the output voltage. Actually, if the peak primary current is fixed, the converter behaves as a constant power generator. Therefore, a modulation of the peak primary current versus output voltage must be done in order to get the constant output current characteristic. A conventional way consists to use an optocoupler between primary and secondary, with additional circuitry on secondary side (Reference, error amplifier and current sense resistor). This device avoids the use of all the secondary circuitry by controlling from primary side the secondary average output current. Figure 12 presents the internal constitution of the current control function. It is built around a constant current source Iref, and a mosfet switch driven with the complemented signal EOD, in series with a resistance R. The middle point of these elements is available on the CREF pin. The EOD signal is generated by the demagnetisation function, which is monitoring the voltage of the main transformer auxiliary winding.
CONSTANT OUTPUT CURRENT The power topology to be used with this device is a simple discontinuous flyback, as shown on figure 10. The average output current of such a
Figure 12: Constant Current Operation
+Vin n Is D1 IOUT C1 GND D2
Ip VCREF Tsw
R1
Ip T
RS
VCC Iref
DSENSE Demag.
DRAIN
Is
t
Oscillator
n. VCREF RS
EOD R C2
t
PWM Latch
Q R
EOD 1
CREF
+ GND CS ENSE VIPer31 SOURCE
t 0 Ic Iref tonsec t
Ic Uc C
R2 RS
Iref Uc R
SC12140
10/16
VIPER31SP
An external resistance R1 is needed to withstand the negative voltage generated by the winding. As long as the transformer is delivering some energy on secondary side, the negated EOD signal remains in the high state and the mosfet switch Q is on. The duration of this state is noted tonsec and corresponds to the time where the secondary current is flowing through D1. For details about the demagnetisation function, refer to figure 6. The average output current can be expressed as: The product R x IREF This product corresponds to a voltage which is noted Vreg in the specification tables. Figure 5 shows the test fixture for measuring it : The DSENSE pin is held in the high state (In fact, it is left open, as an internal pull up current source is internally connected on this pin) and the mosfet switch Q is always in the high state. In this case, the voltage on the CREF pin establishes at R x IREF . Note that the oscillator must be running for the demagnetisation block to sample correctly the DSENSE pin. As Vreg has a typical value of 350 mV, the output current can be finally written as : 0.175 IOUT = n x
IOUT =
IS tONSEC X 2 TSW
(1)
Where : IS is the peak secondary current. tONSEC is the conduction time on secondary side. TSW is the switching period. Taking into account the transformer ratio n between primary and secondaryside, IS can also be expressed versus primary peak current IP : IS = n x IP (2) The value of the capacitor C is sufficiently high to consider the voltage Uc as constant. This capacitor is submitted to a charging current and discharging current at the rhythm of the switching frequency. As these currents are in the range of a few mA (Iref is typically 1 mA), a 470 nF is a suited value for a switching frequency of 60 kHz. In steady state, it can be written that the charge is equal to the discharge : UC IREF x (TSW - t ONSEC) = ( - IREF ) x t ONSEC R It comes : TSW UC = R x IREF x (3) tONSEC As UC can be considered as a constant voltage, can be also expressed as : UC IP = (4) RS Combining (1), (2), (3) and (4) : R x IREF n IOUT = x 2 RS This last expression shows that the average output current doesn't depend any more neither on the output voltage, nor on the duty cycle, nor on the input voltage. The only parameters which are setting its value are : The transformer ratio n. The sense resistor value RS
RS
A sense resistor of 1.3 with a transformer ratio of 6 gives a typical output current of about 800 mA. The schematics of figure 10 shows a compensation on the CSENSE pin with the two resistances R5 and R7. These resistances are connected on the Vin input voltage and are providing an offset on the current sense pin. The higher is the input voltage, and the higher is this offset current. The purpose of this compensation is to cancel the effect of the current control propagation time td, which induces an extra current on top of the theoretical peak current Ip given by (4). The output current obtained with this compensation can be seen on figure 11. The typical "flatness" is about +/-2.5 %, including the input voltage variation from 100 VDC to 400 VDC. If less accuracy is needed, these two resistances can be omitted. CONSTANT VOLTAGE OPERATION An another part of the circuit is in charge of the regulation of the output voltage, and generates the vertical characteristic of figure 11. It consists of a primary feedback regulation, with a conventional voltage mode control : An operational amplifier with an internal voltage reference of 2.6 V is configured in error amplifier and defines the duty cycle of the power mosfet switch by comparison with the oscillator sawtooth (See block diagram on page 1). As it is a primary feedback, the accuracy of the output voltage depends closely on the transformer coupling quality. This is especially
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VIPER31SP
true for low output current where the output voltage can reach high values, as shown on figure 11 : 20 V can be reached for a nominal regulated one of 14.5 V, with a typical transformer. But a simple clamping zener can limit it to about 17 V with a reasonable dissipated power. The 10 % to 100 % output load regulation is better than +/-7 %. COMPONENTS SIZING The following procedure defines the value of essential parameters for the transformer and the sensing resistance in a typical application. The user can adapt by himself the final design, according to specific needs, if any.
TSW is the switching period.
START UP SEQUENCE An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitors connected to the VDD and VCC pins. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 13. The sum of the external capacitors CSTART on the VDD and VCC pins must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, capacitor value implemented on the CREF pin (See soft start consideration here after). The following formula can be used for defining the minimum capacitor needed : IDD x tSS CSTART > where : VDDhyst IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. CSTART = CVDD + CVCC is the sum of both capacitors on VDD and VCC pins. Once is defined, allot a standard 4.7 F / 16 V on the VDD pin, and the rest on the VCC pin. The VDD capacitor insures a correct decoupling of the internal serial regulator between VCC and VDD. Soft start feature is implemented through the CREF capacitor which is also filtering the CREF voltage. The minimum value of this capacitor has to be set according to the switching frequency, in order to filter the charging and discharging current issued from the CREF pin (Refer to the current control description part). It can be increased from
- 1. Define the maximum output voltage
MAX for which the converter has still to OUT operate in constant current mode. V
- 2. Check that the ratio between the minimum
MIN MAX and V is OUT OUT lower than 2.5. This ratio is limited by the overvoltage protection value (Typically 29 V) and VDDreg (Typically 10 V) and their tolerances.
operating output voltage V
- 3. Compute the transformer turn ratio n from
primary to secondary with the formula : np 100 n= = MAX ns V OUT
- 4. Compute the sense resistance value with the
formula :
RS = n x
0.175 IOUT
- 5. Compute the transformer turn ratio nAUX
from auxiliary to secondary with the formula : na 25 nAUX = = MAX ns V OUT
- 6. The current control function requires the
converter to work in discontinuous mode. The primary inductance value LP of the transformer can be computed by respecting this constraint in all conditions, or by using the following MIN V x TSW n IN formula : LP = x where : 10 IOUT MIN V is the minimum input rectified DC voltage IN from the mains.
12/16
VIPER31SP
Figure 13: Start Up Circuit and Sequence
2 mA VCC LDO Reg. AUXILIARY WINDING CVCC CVDD VDD ON/OFF UVLO LOGIC + Ref VIPer31
DRAIN
(V)
VCC
VDDreg VDDon VDDoff tss
VDD
GND
SOURCE t
SC12150
this value to provide a soft start feature, of which the duration depends on some circuit parameters, like transformer ratio, sense resistor, output capacitors and load. The user will define the best appropriate value by experiments. SHORT CIRCUIT OPERATION In case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the VCC pin (i.e. short circuit on the output of the converter), the external capacitors discharge themselves down to the low threshold voltage VDDoff of the UVLO logic, and the device get back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. The converter enters a endless start up cycle, with a start-up Figure 14 : Short circuit operation
VDD VDDon VDDoff
duty cycle defined by the ratio of charging current towards discharging when the VIPer31 tries to start. This ratio is fixed by design to 1.5 to 12, which gives a 11% start up duty cycle, while the power dissipation at start up is approximately 0.6 W, for a 230 Vrms input voltage. The average output short circuit current is the product of the start up duty cycle by the output current flowing during the active phase of the device (See figure 14). This output current is limited by either the CREF pin voltage, or the internal current limitation of 1.3 A. These values together with the low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit.
t
Iout Isc
Average output current t
SC12160
13/16
VIPER31SP
OVERVOLTAGE PROTECTION If the output voltage accuracy is not a concern, but only a limitation is desired, the internal overvoltage protection can be used. In this case, five components can be taken out from the schematics of figure 10 (R3-R10-R6-C4-C5) and the input pin FB of the error amplifier is simply grounded. The internal overvoltage protection will act as soon as the VCC voltage reaches typically 29 V, by turning off the power mosfet switch. An hysteresis of about 3 V will enable again the switching of the device at a lower voltage level on the VCC pin. This results in an efficient voltage limitation, in a burst mode operation type, with some ripple on the output. Case by case experiments will define the correct value of output capacitor C3, according to the loading current in low output power condition. STANDBY MODE The standby mode is represented by a very low output current, corresponding to a full loaded battery in a battery charger application. The output voltage is limited by either the overvoltage protection or the error amplifier, according to the design. This results into different situations :
- In case the overvoltage protection is used, the
burst mode operation as described previously takes place, governed by the hysteresis of the overvoltage comparator.
- If the error amplifier is used, many situation can
occur, depending on the compensation network foreseen by the designer. These situations can range from a normal continuous operation, to burst mode. In any case, the output voltage will be regulated to the desired value. Note that the burst operation is providing a very low input power consumption, because it reduces the switching frequency, and thus commutation losses. Less than 1 W of input power can be observed in this operative mode, with a few hundreds of mW delivered to the secondary load. This is far compliant with standby standards, like the "Blue Angel" one.
14/16
VIPER31SP
Power SO-10 MECHANICAL DATA
DIM. MIN. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q 0
o
mm TYP. MAX. 3.65 0.10 0.60 0.55 9.60 7.60 9.50 7.40 7.60 6.35 6.10 1.27 1.25 13.80 0.50 1.20 1.70 8o 1.80 0.047 1.35 14.40 0.049 0.543 MIN. 0.132 0.000 0.016 0.013 0.370 0.291 0.366 0.283 0.283 0.240 0.232 3.35 0.00 0.40 0.35 9.40 7.40 9.30 7.20 7.20 6.10 5.90
inch TYP. MAX. 0.144 0.004 0.024 0.022 0.378 0.300 0.374 0.291 0.300 0.250 0.240 0.050 0.053 0.567 0.002 0.071 0.067
B
0.10 A B
10 = H = A F A1 =
6
=
=
=
E = 1 5 e
0.25
M
=
E2
E3
E1
E4
=
=
A
=
SEATING PLANE DETAIL "A" Q
B
C
h
D = D1 = = = SEATING PLANE
= A1 L
DETAIL "A"
0068039-C
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VIPER31SP
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A . ..
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